The present invention relates to a testing technology in the manufacturing process of a semiconductor apparatus.
General tests conducted in the manufacturing process of a semiconductor apparatus are described referring to FIG. 8.
A functional test and a scan test are conducted in the manufacturing process of the semiconductor apparatus.
The functional test is a test method in which a test vector is provided for a data input 8, logic calculation is exercised in combining circuits 3, 4 and 5, and a data output 9, which is the result of the logic calculation, is compared to an expected value, thereby detecting faults.
In contrast to that, in the scan test, flip-flops are randomly combined by means of scan chains independently from normal operation. In scan test mode, test data is shift inputted from a scan input 6, and values are set in the respective flip-flops. After the setting, clocks are input in normal operation mode, and a combining circuit sandwiched by the flip-flops in front and behind thereof is tested. Again in the scan test mode, the data is shift outputted from a scan output 7 to be compared to the expected value, thereby detecting faults in the combining circuit.
However, in the described testing methods, it is difficult to achieve compatibility between the fault detection with a high fault detection rate and the fault detection at the actual operating speed because of the following two reasons.
Reason 1
The implementation of the functional test covers a variety of statuses subject to interinstruction dependences and dependences resulting from different data combinations, and further, timings at which interruptions, exception processing and the like are combined. It is, however, actually difficult to test all the described statuses in terms of creating test patterns and also implementing such tests. In brief, there is a limit to the improvement of the fault detection rate.
Reason 2
The scan test is generally implemented at a speed lower than the actual operating speed, which precludes the possibility of detecting delay faults. Hypothetically, when the scan test is implemented at the actual operating speed, the toggle rate of the flip-flops (activation rate) becomes unimaginably large compared to the same in the normal operation allowing excessive current flow because all of the flip-flops are randomly combined. The excessive electric flow causes significant reduction of a power-supply voltage (IR-Drop), which subsequently causes a lowered speed of a transistor making it difficult to detect the delay faults. As a result, the delay fault detection cannot be implemented at the actual operating speed in the scan test.